In recent years, an operating voltage of a semiconductor device has been gradually decreasing so as to reduce power consumption of the semiconductor device. Currently, some semiconductor devices use quite low operating voltages of about 1 volt. If the operating voltage decreases, it is necessary to reduce a threshold voltage of each transistor accordingly. As a result, a sub-threshold current flowing through the transistor in an off state disadvantageously increases. To solve such a problem, a method of dividing power supply wirings into a main power supply wiring and a pseudo power supply wiring have been proposed in Japanese Patent Application Laid-open Nos. 2000-13215 and 2000-48568.
FIG. 7 is a circuit diagram of a conventional semiconductor device using pseudo power supply wirings.
A circuit shown in FIG. 7 includes a circuit block 10 configured to include four stages of inverters 11 to 14. The circuit block 10 is a block the logic of which is fixed in a standby state. In the example shown in FIG. 7, a signal IN input to the circuit block 10 is fixed to high level in the standby state. Needless to say, a logic value of the input signal IN is appropriately changed into an active state.
Three power supply wirings, that is, a main power supply wiring VDD and a pseudo power supply wiring VDT to each of which a power supply potential is supplied, and a main power supply wiring VSS which a ground potential is supplied are provided for the circuit shown in FIG. 7. A P-channel MOS transistor 20 is provided between the main power supply wiring VDD and the pseudo power supply wiring VDT, and a standby signal ST is supplied to a gate electrode of the P-channel MOS transistor 20.
The standby signal ST is a signal that becomes high level when the circuit block 10 is set in the standby state, and kept to be low level when the circuit block 10 is in the active state. Due to this, in the active state, the main power supply wiring VDD is short circuited to the pseudo power supply wiring VDT via the transistor 20. On the other hand, in the standby state, the transistor 20 is turned into off state. Due to this, the pseudo power supply wiring VDT is disconnected from the power supply wiring VDD. As a result, the power supply potential is hardly supplied to the circuit block 10.
Moreover, among the four inverters 11 to 14 included in the circuit block 10, the first inverter 11 and the third inverter 13 are connected between the pseudo power supply wiring VDT and the main power supply wiring VSS. Further, the second inverter 12 and the fourth inverter 14 are connected between the main power supply wiring VDD and the main power supply wiring VSS. As described above, in the active state, the main power supply wiring VDD is shorted to the pseudo power supply wiring VDT. Accordingly, a power supply voltage is correctly applied to both power supply terminals of each of all the inverters 11 to 14, whereby the circuit block 10 can operate normally. Therefore, a signal OUT output from the circuit bock 10 has a correct value according to the logic value of the input signal IN.
Meanwhile, in the standby state, the pseudo power supply wiring VDT is disconnected from the main power supply wiring VDD. Accordingly, the power supply potential is hardly supplied to sources of P-channel MOS transistors 11p and 13p included in the first inverter 11 and the third inverter 13, respectively.
Nevertheless, because the input signal IN is fixed to the high level in the standby state, transistors that are included in the inverters 11 to 14 and that are turned into on states are fixed to an N-channel MOS transistor 11n, a P-channel MOS transistor 12p, an N-channel MOS transistor 13n, and a P-channel MOS transistor 14p shown in FIG. 7, respectively. Furthermore, sources of these transistors 11n, 12p, 13n, and 14p are connected to the main power supply wiring VDD or VSS, so that the logic of the circuit block 10 is maintained correctly in the standby state.
On the other hand, sources of the P-channel MOS transistors 11p and 13p that are turned into off states in the standby state are connected to the pseudo power supply wiring VDT disconnected from the main power supply wiring VDD. Due to this, sub-threshold current hardly flows through the P-channel MOS transistors 11p and 13p. It is thereby possible to reduce the power consumption while the circuit block 10 is in the standby state.
However, even at the time of standby state, the pseudo power supply wiring VDT and the main power supply wiring VDD are not completely cut off, and by the sub-threshold current that passes in the P-channel MOS transistor 20, a slight amount of current continues to be supplied to the pseudo power supply wiring VDT. Thus, the sub-threshold currents in the P-channel MOS transistors 11p and 13p are not completely rendered zero, and the sub-threshold current that passes in the P-channel MOS transistor 20 results in flowing into the P-channel MOS transistors 11p and 13p. 
When a transistor size is rendered small, the sub-threshold current can be reduced. However, a drive capability sufficient for operating the circuit block 10 is required in the P-channel MOS transistor 20 at the time of active state. Thus, it is fundamentally difficult to render the transistor size small.
Methods for reducing the sub-threshold current that passes in the pseudo power supply wiring VDT at the time of standby state can include a method in which instead of the P-channel MOS transistor 20, an N-channel MOS transistor is used so that the gate electrode of the N-channel MOS transistor is reverse-biased with respect to the source electrode at the time of standby state.
However, if the main power supply wiring VDD and the pseudo power supply wiring VDT are connected by the N-channel MOS transistor, it is needed to supply a gate electrode with 2×VDD of a high potential at the time of active state. A signal of such a level can be generated by using a level conversion circuit or the like. However, when the signal is passed through the level conversion circuit, the signal is slightly delayed. As a result, there occurs another problem in that a timing of switching the circuit block 10 from the standby state to the active state is delayed.